Litho Node and Moore’s Law

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Litho Node and Moore’s Law
(09/21/07 – Rev 0)



The recent 2007 spring IDF saw an appearance of a pioneer within the microelectronics industry. One who is famed for the law named after him, Gordon Moore. Such a prominent figure, even in retirement, speaking in such a large public venue will generally garner headlines on most major news sites and in many journalistic writings. In his appearance Moore has reached beyond his initial work and predicted yet again… the end of his own law, the end of Moore’s law. This should surprise nobody, as there must be a physical limit to which a transistor may shrink, , ohowever in the discussions that always ensue after such a statement cannot help but be taken aback by the number of people who misunderstand the concept of Moore’s Law and the consequences it brings to the industry. More specifically, it is clear that a great majority of people simply do not understand what compaction really means, at least from the Moore’s Law prespective. Worse however are that many fail to understand the basics of what the ‘litho node’ actually represents.

This brief article is not intended to discuss in any detail the trials and limitations on device scaling, rather it is intended to clarify some very common misunderstandings of the dimensions that are discussed when technology is discussed with respect to the litho node. What does the 65 nm mean when we refer to a 65 nm CPU? Where do these numbers come from and why do they so oddly shrink down as they do?

Litho Node Defined

So what exactly does 65 nm CPU mean? When one uses in speech ‘90 nm node’, what does it represent really? The answer is quite easy, and the common definition can be found in the ITRS executive summary. The ITRS is the International Technology Roadmap for Semiconductors, which is a commission, established through representation of key technology companies – chip makers, equipment makers, and design centers — across the globe (ITRS). Their job is to establish a guideline or roadmap for key milestones, identify problem areas and roadblocks for achieving such goals, and defining a common point of reference by which all companies may expect the industry to move.

The definition of the lithography node is quite straight forward. In simplest terms, it is the distance that would make ½ the pitch between the two closes parallel running metal lines that occur in the first metal contact layer for the device (ITRS 2005 Roadmap, see page 5/6 ). This may appear somewhat esoteric, but is it quite easy to visualize with a simple diagram, which is shown in the executive summary of the 2005 ITRS roadmap. A rough example is shown below, figure 1.

Many references to the process technology size often uses this number to describe “the smallest feature” or “the width of the narrow wires in the CPU”. As you can see from the formal definition, neither is actually true. The smallest feature is actually the gate electrode, which as a rule of thumb is between 1/3 to 1/2 the process node as referenced. At 65 nm both AMD and Intel have published gate length (the distance between source (S) and drain(D)) of 35 nm or roughly about 1/2 of the node. At 90 nm, this distance was about 40 to 45 nm depending on the company.

Litho node in relation to die size

Over the course of time, process technologies have progressed by a strange series of different dimensions, actually not strange but not straight forwardly obvious. Early in history of the industry, the litho node was referenced in units of microns, to facilitate the discussion, all nodes will be referenced in nanometers, as such the 1 micron technology is actually 1000 nm, or the 0.25 micron technology is actually 250 nm. Providing this detail makes it much easier to see how the progression emerges. Starting with 1 micron or 1000 nm the process technology has followed the progression as such


  • 1000 nm (1 micron)
  • 700 nm (0.7 micron)
  • 500 nm (0.5 micron)
  • 350 nm (0.35 micron)
  • 250 nm (0.25 micron)
  • 180 nm (0.18 micron)
  • 130 nm (0.13 micron)
  • 90 nm (all references to micron dropped)
  • 65 nm
  • 45 nm
  • 32 nm (future)
  • 22 nm (future)
  • 15 nm (future)

Other nodes that do not follow this trend are not uncommon, for instance GPU makers and their foundary partners will sometimes split the difference and work toward a slightly more granular cadence, for example 55 nm instead of 45 nm; however, for CPUs, and many other devices, this has been the overall progression. Notice none of the nodes, one from the next, is half of the other. The actual factor is not 0.5 but 0.7, for example… 90 nm is about 0.7 of 130 nm and 45 nm is about 0.7 of 65 nm and so forth and so on. The node definition compacts the scale in one dimension, as s result a direct scaling of the photolithography node to die area is in appropriate. A 0.7 scaling along one direction, to keep the aspect ratio appropriate, must accompany a 0.7 scaling along the orthogonal direction. As such, the area scales not as 0.7 but as 0.49 or (0.7)^2 . This is not by coincidence, rather the scaling factor for any dimension was simply chosen as the square root of 0.5 or roughly 0.7 to ensure that each new technology would scale the area by a factor of 0.5.


Moore’s Law and Transistor Density

The most commonly misunderstood concept in the semiconductor industry to a common observer is Moore’s Law. One will often read Moore’s Law quoted as “the number of transistors on a chip will roughly double every 2 years”. Before connecting Moore’s law into the concept of litho node, a bit of history is in order.

Gordon Moore, together with Robert Noyce, founded what has become today as the largest semiconductor manufacturer in the world. Though Intel incorporated in 1968, Moore was a prominent figure in the engineering and academic circles of this fledgling industry. Moore was invited to present a paper in which he was asked to predict the progress semiconductors over the next 10 years, in 1965 he published his work where he concluded that the number of transistors would double each year. At the end of that 10 year, Moore was again invited to present a paper on the accuracy of his prediction and to comment on the current progress; in 1975 he published another


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