Sneak peak at AMD Shanghai - No clock speeds shown

[GeorgeOu]

Charlie shows some pictures here. I am guessing he got the sneak peak at CeBIT. I was there but I guess AMD only showed it to a limited number of people.
Shanghai pictured - The INQUIRER


I posted on it here and pointed out that "We also need to put this in the context of Barcelona having a targeted clock speed of 2.8 GHz according to papers presented at ISSCC 2007 though actual production speeds have yet to exceed 2.3 GHz."

One other interesting note is the reversing of positions in 2009 on the usage of "glue".

"One other interesting note is that AMD’s Montreal 8-core processor due out after Shanghai will resort to MCM (Multi Chip Module). Montreal will be two Shanghai cores glued on to a single processor package. That means AMD will be adopting the same strategy Intel has been using on its 65nm and first-generation 45nm processors where you take two smaller cores and “glue” them on to a CPU package to have more cores per processor. Ironically, Intel will be going the opposite direction starting with Intel Nehalem. Not only will the initial Nehalem-EP 8 MB L3 cache quad-core processor be single-die, but even the much larger Nehalem-EX 8-core processor with 24 MB L3 cache will be single-die. So in 2009, watch for both companies to reverse their marketing literature touting or disparaging MCM “glue” technology."

[Simul4ti0n]

I think it's a good move for AMD to go with MCM from now on. It's just too many cores for Monolithic.

[MeltDown]

Regarding MCM versus native, my view remains the same as it is now. I don't care if there are 1, 2, 4, or 348 (or any other number) pieces of silicon under the heat spreader, all that matters are three key parameters: performance, power consumption, and price.

[arisythila]

I wonder how they are going to pull that off tho. MCM that is.

I remember reading that there was a reason they didn't do MCM from the start. (Because how HTT is)

This is pretty awesome tho. I see its still 1207 If they are not too expensive, I will grab some for my winblows server :-)

[SK711G]

So... AMD got it to run Windows, Task Manager, as well as CPU-Z(censored). Well thats good news.

[GeorgeOu]

Originally Posted by arisythila

I wonder how they are going to pull that off tho. MCM that is.

I remember reading that there was a reason they didn't do MCM from the start. (Because how HTT is)

This is pretty awesome tho. I see its still 1207 If they are not too expensive, I will grab some for my winblows server :-)

They're planning to split the channels. One controller on one die will handle one channel while the other handles the other channel.

[GeorgeOu]

Originally Posted by MeltDown

Regarding MCM versus native, my view remains the same as it is now. I don't care if there are 1, 2, 4, or 348 (or any other number) pieces of silicon under the heat spreader, all that matters are three key parameters: performance, power consumption, and price.

Native is always better IF you can yield high clock speeds and IF your margins on the chip can justify your yields). AMD couldn't get sufficient yields for high clock speeds and couldn't get a high enough selling price to cover their production costs for Barcelona and it hurt them. Their execs have clearly stated that if they could have done it all over again, they would have gone MCM with Barcelona.

Intel execs have also clearly stated that native quad core is better if you can get the high yield and clock speeds but that they weren't confident enough with 65nm and first-year 45nm to produce the desired yields and clock speeds. However, they are confident enough in their second generation 45nm process to do native quad- and eight-core.

[Sirrobin4ever]

Originally Posted by GeorgeOu

They're planning to split the channels. One controller on one die will handle one channel while the other handles the other channel.

So theoretically, it could do quad channel ram as well?

[Clue69Less]

Originally Posted by GeorgeOu

Native is always better IF you can yield high clock speeds and IF your margins on the chip can justify your yields).

I haven't seen enough data to come to such a conclusion and I don't know where you're getting your data. I just can't see it. Right now, as you know, the top performing quads are Intels and they are glued. I haven't seen a native quad that does have the high clock speed to make a valid comparison to the glued Intels. I also don't think that we can assume that the native versus glued dual core performance database will translate to quads, let alone octas and above. Nehalm will give more clues to the puzzle, but at this point we need some history to unfold in the design and execution of Intel and AMD arch but that implies that AMD will survive long enough to evolve further...

Note that I will not be surprised if the future proves your comment to be true but I'm thinking that we might be a another generation or two away from designers coming to grips with improved arch designs for native quads. I also forsee that each bump in 2 to the nth number of cores will have significant new learnings for reaching the processing potential for a specific fab spec. And all of this topic really hinges on software development and there certainly is lag happening in that field.

[GeorgeOu]

Originally Posted by Clue69Less

I haven't seen enough data to come to such a conclusion and I don't know where you're getting your data. I just can't see it. Right now, as you know, the top performing quads are Intels and they are glued. I haven't seen a native quad that does have the high clock speed to make a valid comparison to the glued Intels.

You're making a fundamentally incorrect assumption here. You're assuming that just because a glued 65nm Clovertown quad-core is faster clock-for-clock than a Barcelona quad-core on SPECint_rate2006 @ lower than 2.6 GHz clock speeds, then native quad-core did AMD Barcelona no good.

Native quad-core DID deliver lower memory latency for AMD's Barcelona processor, but it came at a cost of lower yields and lower clock speeds. To make things worse, Barcelona had a smaller cache and I understand the L3 cache wasn't very fast. All these factors neutralized the benefits of being native quad-core.

Intel's Clovertown architecture was fast INSPITE of the lack of an on-chip memory controller and INSPITE of being "glued" together. That's because the massive cache and the wider execution engine of Core 2 architecture overcame these memory technology deficiencies.

It’s not a “theory” that single-die architecture delivers lower latency; it’s simply a fact. The question is whether you can overcome the engineering challenges of producing a massive chip and whether you can do it without sacrificing too much clock speed. Your yields also need to be justified by your selling price.

[Mandrake]

Quad channel ram seems likely for this. Two 128bit memory controllers would give you quad channel memory alright.

[JKflipflop]

Originally Posted by arisythila

I wonder how they are going to pull that off tho. MCM that is.

I remember reading that there was a reason they didn't do MCM from the start. (Because how HTT is)

This is pretty awesome tho. I see its still 1207 If they are not too expensive, I will grab some for my winblows server :-)

Couldn't they just fake a MP server by directly connecting the HTT links between the two die? If you can do it across multiple sockets, I see no reason why this is any different.

[qcmadness]

Originally Posted by GeorgeOu

They're planning to split the channels. One controller on one die will handle one channel while the other handles the other channel.

This will cause a tremendous increase in memory latency, as the 4x4 did.

[1Tanker]

I guess Intel can pass this back to AMD:

[Mandrake]

How about 'Making profit for dummies' or 'Releasing products on time for dummies'?

[beerandcandy]

Originally Posted by 1Tanker

I guess Intel can pass this back to AMD:

lol

[turboflame]

Originally Posted by GeorgeOu

They're planning to split the channels. One controller on one die will handle one channel while the other handles the other channel.

So in order to use the MCM chips the user is required to use a dual channel setup regarding RAM?

And each chip can't share RAM with the other because it's on a separate channel (like the 4x4)?

Sounds pretty problematic.